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maxim integrat ed products 1 some revisions of this device may incorporate deviations from published specifi cations known as errata. multiple revisions of any device may be simultaneously available through various sales channels. f or information about device e rrata, go to: www.maxim - ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1- 888 - 629 - 4642, or visit maxims website at www.maxim - ic.com. DS33M30/ds33m31/ds33m33 ethernet over sonet/sdh mapper ________________________ general description the DS33M30 family of products provides a compact and efficient solution for transporting gigabit ethernet traffic over oc - 3/stm - 1 optical networks. with the addition of an optical transceiver, ethernet phy, ddr sdram, and host processor, a complete solution of gbe over oc - 3/stm - 1 can be implemented. the family supports ethernet over sonet/sdh (eos) at vc - 4, next - generation eos high - order mapping with multiple concatenated vc- 3s, and ethernet over pdh over sonet/sdh (eopos) with up to three virtually concatenated ds3/e3 tributaries. the supported frame encapsulations include gfp - f, hdlc, chdlc, and x.86 (laps). _______________________________ applications ethernet service delivery over sonet/sdh multiservice provisioning platforms (mspps) transparent lan services lan extension _____________________________________features ? support for eos in one sts - 3c/vc - 4, eos over up to three concatenated sts - 1/vc - 3s, and eopos over up to th ree concatenated ds - 3s ? two independent 155.52mbps serdes ports ? one 10/100/1000 ieee 802.3 ethernet mac port ? configurable mii/rmii/gmii mac interface ? gfp/laps/hdlc/chdlc encapsulation ? ieee 802.1q vlan and q - in - q support ? add/drop oam frames from p interface ? quality of service (qos) support ? traffic policing through cir/cbs ? classification through pcp or dscp ? supports up to 512mb ddr sdram buffer ? spi and parallel microprocessor interfaces ? 1.8v, 2.5v, 3.3v supplies features continued in section 1 . _________________________ functional diagram ____________________________________________________________ ordering information/selector guide part supported eos/eopos modes 155mbps ports ext. ds3/e3 li ne pin - package DS33M30 n+ eos at vc -4 1 no 144 csbga ds33m31 n+ eos at vc - 4, eos at 3xvc - 3, eopos at 3xds3 2 no 256 csbga ds33m33 n+ eos at vc - 4, eos at 3xvc - 3, eopos at 3xds3 2 yes (3) 256 csbga + denotes a lead (pb) - free/rohs - compliant package. rev 1; 010809 vcat / lcas ds3/e3 framers gfp / hdlc / laps traffic mgmt advanced oam ethernet mac high - order mapper framer b 3x vc -3 3 serdes a DS33M30/m31/m33 3 ds3 add/drop (ds33m33 only) 1 vc -4 serdes b serdes b and framer b on (ds33m31/33 only) framer a downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 2 of 21 table of contents 1. general description and feature highligh ts ........................................................... 4 1.1 d evice f eature o verview ........................................................................................................ 5 1.2 tdm f eature o verview ............................................................................................................ 6 1.3 sonet/sdh ............................................................................................................................... 7 1.3.1 sts- 3/stm - 1 serdes ....................................................................................................................... 7 1.3.2 sts- 3/stm - 1 framer and formatter ................................................................................................ . 7 1.3.3 sts- 3c/au - 4 pointer processing ...................................................................................................... 8 1.3.4 sts- 3c spe/vc - 4 path termination ................................................................................................ . 8 1.3.5 sts- 3 mux/demux (ds33m31 and ds33m33 only) .......................................................................... 8 1.3.6 sts- 1/au - 3/tu - 3 formatter and framer (ds33m31 and ds33m33 only) ......................................... 9 1.3.7 sts- 1/au - 3/tu - 3 pointer processing (ds33m31 and ds33m33 only) .............................................. 9 1.3.8 sts- 1/vc - 3 path termination (ds33m31 and ds33m33 only) ........................................................ 10 1.4 pdh (ds33m31 and ds33m33 o nly ) ...................................................................................... 12 1.4.1 add/drop ds3/e3 framer/formatter (ds33m31 and ds33m33 only) .............................................. 12 1.4.2 ds3/e3 ethernet mapping (ds33m31 and ds33m33 only) ............................................................. 13 1.4.3 line ds3/e3 framer/formatter (ds33m33 only) ............................................................................. 13 1.4.4 loopback ........................................................................................................................................ 14 1.5 v irtual c oncatenation (vcat) (ds33m31 and ds33 m33 only ) ........................................... 14 1.5.1 sonet/sdh vcat/lcas .............................................................................................................. 14 1.5.2 pdh vcat/lcas ........................................................................................................................... 15 1.6 e ncapsulation ........................................................................................................................ 15 1.6.1 gfp - f encapsulation (per itu - t g.7041) ....................................................................................... 15 1.6.2 hdlc encapsulation ....................................................................................................................... 15 1.6.3 chdlc encapsulation ..................................................................................................................... 15 1.6.4 x.86 encapsulation support ............................................................................................................ 15 1.7 e thernet f eature o verview .................................................................................................. 15 1.7.1 ethernet mac interface ................................................................................................................... 16 1.7.2 ethernet bridging for 10/100 ............................................................................................................ 16 1.7.3 ethernet traffic classification .......................................................................................................... 16 1.7.4 ethernet traffic profiling and policing .............................................................................................. 16 1.7.5 ethernet traffic sched uling ............................................................................................................. 16 1.7.6 ethernet control frame processing ................................................................................................ . 16 1.7.7 q- in -q ............................................................................................................................................. 16 1.8 sdram i nterface ................................................................................................................... 16 1.9 c lock r ate a dapter (clad) .................................................................................................. 16 1.10 spi s erial m icroprocessor f eatures ............................................................................... 17 1.11 p arallel m icroprocessor i nterface (ds33m31 and ds33m33 o nly ) ............................. 17 1.12 t est and d iagnostics .......................................................................................................... 17 2. standards compliance ...................................................................................................... 18 3. applications .......................................................................................................................... 20 4. revision history ................................................................................................................... 21 downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 3 of 21 list of figures figure 1 - 1 tdm functional blocks ......................................................................................................................... 6 figure 3 - 1. example application 1: eos for DS33M30 .......................................................................................... 20 figure 3 - 2. example application 2: eopos for ds33m31 interworking with eop in ds33x162 family of devices . 20 figure 3 - 3. example applicatio n 3: eopos transport for ds33m33 with integrated ethernet and pdh services ... 20 list of tables table 1 - 1. product selection matrix ........................................................................................................................ 5 table 1 - 2. summary of mapping functions ............................................................................................................ 5 table 2 - 1. standards compliance summary ........................................................................................................ 18 downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 4 of 21 1. general description and feature highlights th e DS33M30 family of devices provides interconnection and mapping functionality between ethernet and sonet/sdh networking elements. the product family includes three devices with differing fea tures: ? DS33M30: one gmii mapped to sts - 3c/vc - 4 in a compact 10mm package. ? ds33m31: one gmii/mii mapped to a protected interface, with higher order eos and eopos. ? ds33m33: one gmii/mii mapped to a protected interface, with higher order eos, eopos and ds3/e3 add/drop mux. all devices in the product family contain an ethernet mac port, one or two sts - 3/stm - 1 serdes ports with the lvds/lvpecl interface, one or three gfp - f/hdlc/chdlc/x.86 (laps) protocol encapsulators, one or three higher order sonet/sdh mappers, a ddr sdram interface, and a local bus port for control/status . ethernet traffic is encapsulated with gfp - f, hdlc, chdlc, or x.86 (laps) protocol to be transmitted onto the sts - 3/ stm- 1 interface. the family receives encapsulated ethernet frames from the serdes receiver interface and transmits the de - encapsulated fr ames onto the ethernet port. with the smallest footprint, the DS33M30 contains the smallest feature set in the product family. it perf orms eos higher order mapping of ethernet frames into a single sts - 3c spe or vc - 4. the DS33M30 has one 1000mbps (gbe) port with gmii interface. the DS33M30 supports ethernet oam insert/extract capabili ty, qos priority scheduling, vlan processing, and committed information rate (cir) - based policers for the delivery of carrier ethernet services. the ds33m31 and ds33m33 expand on the features of the DS33M30 with additional mapping capabilities. they support next - generation ethernet over sonet/sdh in virtually concatenated higher order containers as well as ethernet - over - pdh - over - sonet/sdh (eopos) at the ds3/e3 level. they have an ethernet interface that can be configured as a 10/100mbps mii/rmii port or a 1000mbps (gbe) gmii port . they integrate four mapping/demapping functions: ? sonet/sdh mapping: sts - 1/vc - 3 to sts - 3/stm - 1; or tu - 3 to vc - 4 to stm -1 ? pdh mapping: ds3/e3 to sts - 1/vc - 3 (or tug - 3/vc - 4); ? eos higher order mapping: ethernet to sts - 1/vc - 3 (or tu - 3); and ? eopos mapping: ethernet to ds3/e3 to sts - 1/vc - 3 (or tug - 3/vc - 4). at the sts - 3/stm - 1 side, the ds33m31 and ds33m33 devices interface to an sts - 3/stm - 1 signal through dual s erial - data buses operating at the rate of 155.52mbps. this allows the implementation of a protected sonet /sdh at phy layer. each serializer/deserializer ( serdes ) is supported with independent sts - 3/stm - 1 framer. the ds33m33 supports all the features of the DS33M30 and ds33m31, with additional line interfaces for up to three add/drop ds3/e3 tributaries. the serdes interfaces, with lvds/lvpecl, can be seamlessly connected to commercially available optical transceivers. microprocessor control can be accomplished through an 8/16 - bit local bus or spi bus. the family contains a 125mhz ddr sdram controller and interfaces to a 32 - bit - wide 256mb ddr sdram through a 16 - bit data bus. the ddr sdram is used to buffer data through the ethernet and sts - 3/stm - 1 ports. t he power supplies consist of a 1.8v core supply, a 2.5v ddr sdram supply, and 3.3v i/o supply. downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 5 of 21 table 1-1 . product selection matrix part ethernet port sts - 3/ stm - 1 port pdh (ds3/e3) port ethernet mapping vlan forwarding support priority forwarding support vcat groups (vcgs) p control package DS33M30 1 gbe 1 0 eos na y 1 spi 10mm, 144 csbga ds33m31 1 (10/100, gbe) 2 (1+1 protected) 0 eos, eopos y y 3 spi or parallel 17mm, 256 csbga ds33m33 1 (10/100, gbe) 2 (1+1 protected) 3 eos, eopos y y 3 spi or parallel 17mm, 256 csbga note: the number of members for a vcg in the ds33m31 and ds33m33 can be 1, 2, or 3. 1.1 device feature overview note: see the glossary section (in the full data sheet) for the descriptions of terms used in this documentation, especially for the terms referring to the ports, blocks, and directio ns. table 1-2 . summary of mapping functions mapping functions > DS33M30 ds33m31 ds33m33 notes 1 ethern et > sts - 3c > sts -3 x x x 2 ethernet > au - 4 > stm -1 x x x 3 ethernet > sts - 1 > sts -3 x x 4 ethernet > au - 3 > stm -1 x x 5 ethernet > tu - 3 > au - 4 > stm -1 x x 6 ethernet > ds3 > sts - 1 > sts -3 x x without external ds3 port 7 ethernet > ds3 > au - 3 > stm -1 x x 8 ethernet > ds3 > tu -3 > au-4 > stm -1 x x 9 ethernet > e3 > sts - 1 > sts -3 x x without external e3 port 10 ethernet > e3 > au - 3 > stm -1 x x 11 ethernet > e3 > tu -3 > au-4 > stm -1 x x 12 ds3 > sts - 1 > sts -3 x 13 ds3 > au - 3 > stm -1 x 14 ds3 > tu - 3 > au - 4 > stm -1 x 15 e3 > sts - 1 > sts -3 x 16 e3 > au - 3 > stm -1 x 17 e3 > tu - 3 > au - 4 > stm -1 x the DS33M30 family of devices offer the following features: ? supports the mapping protocols as listed in table 1-2 . ? supports single 10/100/1000mbps ethernet interface ? sts- 3/stm - 1 interface operating at 155.52mbps ? supports two transmit timing modes for sts - 3/stm - 1 port(s): ? loop timing (transmi t timing reference = receive timing) ? local timing (transmit timing reference = clad timing) ? supports three transmit timing modes for line ds3/e3 ports: (ds33m33) ? loop timed (transmit timing reference = receive timing) ? line timed (or thru timed) (transmit timing reference = drop ds3/e3 thru timing) ? local timed (transmit timing reference = clad timing) ? certain clock, data, and control signals can be inverted to allow a glueless interface to other devices ? certain port can be put into a low - power standby mode when not being used downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 6 of 21 ? manual or automatic one - second update of performance monitoring counters ? single reference clock for all data rates using internal clock rate adapter (clad) ? detection of loss of transmit clock and loss of receive clock ? supports two packa ges: ? 10mm, 144 - pin csbga package (DS33M30) ? 17mm, 256 - pin csbga package (ds33m31/ds33m33) ? 1.8v, 2.5v, 3.3v supplies ? ieee 1149.1 jtag boundary scan ? software access to device id and silicon revision ? development support includes evaluation kit, driver source code, and reference designs 1.2 tdm feature overview figure 1-1 describes the tdm side feature. figure 1-1 . tdm functional blocks sts-3 section/line termination sts-3 section/line termination mu x sts-3 path termination (vc-4) sts-1 path termination (vc-3) mu x ds3/e3 mapper mu x ds3/e3 desync add/drop ds3/e3 framer line ds3/e3 framer eopos eos (vc-3/sts-1) serdes serdes eos (vc-4/sts-3c) line ds3/e3 side b3zs/ hdb3 line coder mu x to encapsulated ethernet sts-3/stm-1 side drop direction add direction ? supports m23 ds3, c - bit ds3, g.751 e3, and g.832 e3 facilities ? mapping/demapping of three ds3/e3 tributaries to/from sts - 3/stm - 1 through sts - 1 or au - 3 or tu - 3/au -4 ? fully integrated and compliant ds3/e3 mapper/demapper and synchronizers/desynchronizers per telcordia, ansi, and itu standards ? high speed ds3/e3/sts - 1/sts - 3 overhead insertion/extraction with full access to all overhead bytes ? full - featured ds3/e3/sts - 1/sts - 3 defect and performance monitoring (pm) support large pm counters for accumulation intervals up to one second ? loopback capabilities at both sts - 3/stm - 1 side and line ds3/e3 side ? dual sts - 3/stm - 1 155.52mbps serial interfaces with receive clock recovery and transmit clock synthesis ? from a single reference clock the clad ( clock rate adapter) generates clock references for ds3 (44.736mhz), e3 (34.368mhz), and/or sts - 3/stm - 1 reference (77.76/19.44mhz) downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 7 of 21 1.3 sonet/sdh 1.3.1 sts - 3/stm -1 serdes ? serdes with clock recovery at 155.52mbps interface for sts - 3/stm - 1 data stream ? lvds/lvpecl levels for glueless in terconnect to 155.52mbps optical transceiver device 1.3.2 sts - 3/stm - 1 framer and formatter 1.3.2.1 sts - 3/stm -1 formatter with transport overhead insertion ? user - configurable scrambling for transmit sts - 3/stm - 1 bit stream ? user - configurable toh bytes insertion for framing (a1, a2), section trace (j0), section bi p - 8 (b1), section orderwire (e1), section user channel (f1), section data communication channel (dcc) (d1 - d3), sts - 1 pointers (h1, h2, h3), line bip - 8 (b2), automatic protection switching (aps) channel (k1, k2), line dcc (d4 - d12), synchronization status message (s1), line remote error indication (rei) (m1), and line orderwire (e2). note: b1 and b2 are configured as error masks ? automatic calculation and insertion of section bip - 8 (b1) and line bip - 8 (b2) ? user configurable insertion of ais - p, and ais - l ? programmable generation of h1, h2, and h3 bytes as an error mask ? all toh bytes can be inserted from the associated transmit sts - 3 transport overhead input port or software accessible internal registers ? automatic or man ual generation of line remote error indication (rei - l) and line remote defect indication (rdi - l) ? programmable insertion of framing errors, b1 errors, b2 errors, and invalid pointer ? insertion of hdlc data stream into section dcc (d1 - d3), line dcc (d4 - d12), toh dcc (d1 - d12), or section user channel (f1) ? insertion of trace id message into section trace (j0) 1.3.2.2 sts - 3/stm -1 framer with transport overhead extraction ? frame synchronization for sts - 3 compliant to gr - 253 so that sef defect is not detected more than an average of once every six minutes in the presence of sts - 1 ber of 10 - 3 ? optional descrambler of incoming sts - 1 data stream with polynomial of 1+x6+x7 ? extraction of all toh bytes (per lte requirement): framing (a1, a2), section trace (j0) , section bip - 8 (b1 ), section orderwire (e1), section user channel (f1), section data communication channel (dcc) (d1 - d3), sts - 1 pointers (h1, h2, h3), line bip - 8 (b2), automatic protection switching (aps) channel (k1, k2), line dcc (d4 - d12), synchronization status message (s1), line remote error indication (rei) (m1), and line orderwire (e2) ? all toh bytes are presented on the associated receive sts - 3 transport overhead output port and software accessible internal registers ? detection of ste and lte defects including los, lof, sef, cofa, and ais -l ? fully programmable automatic downstream path ais (ais - p) insertion upon detection of los, lof, tim - s, and/or ais -l ? detection of ste and lte defects including rdi - l, aps unstable, and sync message change (s1) ? detection and accumulation of framing errors (a1/a2), oof occurrences, section bip - 8 (b1) errors (bit or block basis), line bip - 8 (b2) errors (bit or block basis), and line remote error indications (rei - l) ? extraction of hdlc data stream from section dcc (d1 - d3), line dcc (d4 - d12), toh dcc (d1 - d12), or section user channel (f1) ? extraction of trace id message from section trace (j0) ? two line bip - 8 parity (b2) bit error rate (ber) measurement circuits with separate software programmable detection and clearing settings downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 8 of 21 1.3.3 sts -3c/au-4 pointer processing 1.3.3.1 sts -3c/au-4 pointer generation ? au- 4 pointer generation using the associated add sts - 3/stm - 1 clock ? pointer generation of outgoing pointer values (h1/h2) per itu g.707 specifications ? generation of au - 4 pointer bytes (h1, h2, and h3) and insertion of the vc - 4 poh ? user - configurable automatic or manual generation of ais -p ? generation of an unequipped indication (all zero path (payload data and poh) with valid j1, b3, and g1) ? comprehensive software programmable pointer (h1, h2) diagnostics 1.3.3.2 sts -3 c/au -4 pointer interpretation ? au- 4 pointer interpretation using the drop sts - 3/stm - 1 clock ? pointer interpretation per itu g.707 specifications ? extraction of au - 4 pointer bytes (h1, h2, and h3) and the vc - 4 poh ? detection of alarm defects including lop and all ones pointer (ais -p) ? detection and accumulation of incoming pointer increments, decrements, changes, and new pointers 1.3.4 sts - 3c spe/vc -4 path termination 1.3.4.1 sts - 3c spe/vc -4 path overhead generation ? generation of all poh bytes including path trace id (j1) , path bip - 8 (b3), path signal label (c2), path status (g1), path user byte (f2), path concatenation indicator (h4), and path growth (z3, z4, and z5) ? all poh bytes can be inserted from either the vc - 4 poh input port or software accessible internal register s ? user configurable automatic or manual generation of pte defects including rdi - p and erdi -p ? programmable error insertion of b3 and rei errors ? insertion of hdlc data stream into path user byte (f2) ? insertion of path trace id into path trace byte (j1) 1.3.4.2 sts - 3c spe/vc -4 path overhead reception and monitoring ? monitoring of all poh bytes including path trace id (j1), path bip - 8 (b3), path signal label (c2), path status (g1), path user byte (f2), path concatenation indicator (h4), and path growth (z3, z4, and z5) ? all poh bytes are presented to the vc - 4 poh output port and software accessible internal registers ? pte defect detection: plm - p, plu - p, uneq - p, pdi - p, rdi - p, and enhanced rdi - p (erdi -p) ? detection and accumulation of path bip - 8 (b3) errors and path rei errors (part of g1) on a bit or block basis ? two poh b3 bit - error rate (ber) measurement circuits with separate software programmable detection and clearing thresholds ? extraction of hdlc data stream from path user byte (f2) ? extraction of path trace id from path trace byte (j1) 1.3.4.3 sts - 3c spe/vc -4 payload mapper/demapper ? mapping of ethernet traffic into/out of vc - 4 payload (c - 4). 1.3.5 sts - 3 mux/demux (ds33m31 and ds33m33 only) 1.3.5.1 sts -3 mux ? multiplexing of three tu - 3 data streams (or ports) into a c - 4 per itu g.707 ? multipl exing of three sts - 1/au - 3 data streams (or ports) into an sts - 3/stm - 1 per itu g.707 and telcordia gr - 253 1.3.5.2 sts -3 demux ? demultiplexing of three tu - 3 data streams (or ports) from a c - 4 per itu g.707 ? demultiplexing of three sts - 1/au - 3 data streams (or ports) f rom an sts - 3/stm - 1 per itu g.707 and telcordia gr - 253 downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 9 of 21 1.3.6 sts - 1/au - 3/tu -3 formatter and framer (ds33m31 and ds33m33 only) 1.3.6.1 sts - 1/au -3 formatter with transport overhead insertion ? user - configurable scrambling for transmit sts - 1 data stream using a polynomial of 1 + x6 + x7 ? generation of all toh bytes (per lte requirement) including framing (a1, a2), section trace (j 0), section bip- 8 (b1), section orderwire (e1), section user channel (f1), section data communication channel (dcc) (d1 - d3), sts - 1 pointers (h1, h2, h3), line bip - 8 parity (b2), automatic protection switching (aps) channel (k1, k2), line dcc (d4 - d12), synchronization status message (s1), line remote error indication (rei) (m1), and line orderwire (e2) note: b1 and b2 are configured as error masks ? calcu lation and insertion of section bip - 8 (b1) and line bip - 8 (b2) ? programmable insertion of ais - p, and ais -l ? programmable generation of h1, h2, and h3 bytes as an error mask ? all toh bytes can be inserted from the associated transmit sts - 1 transport overhead i nput port or software accessible internal registers ? automatic or manual generation of line remote error indication (rei - l) and line remote defect indication (rdi - l) ? programmable insertion of framing errors, b1 errors, b2 errors, and invalid pointer ? inserti on of hdlc data stream into section dcc (d1 - d3), line dcc (d4 - d12), toh dcc (d1 - d12), or section user channel (f1) ? insertion of trace id message into section trace (j0) 1.3.6.2 sts - 1/au -3 framer with transport overhead extraction ? user - configurable descrambler of incoming sts - 1 data stream with polynomial of 1 + x6 + x7 ? extraction of all toh bytes (per lte requirement): framing (a1, a2), section trace (j0) , section bip - 8 (b1), section orderwire (e1), section user channel (f1), section data communication channel (d cc) (d1 - d3), sts - 1 pointers (h1, h2, h3), line bip - 8 (b2), automatic protection switching (aps) channel (k1, k2), line dcc (d4 - d12), synchronization status message (s1), line remote error indication (rei) (m1), and line orderwire (e2) ? all toh bytes are presented on the associated receive sts - 1 transport overhead output port and software accessible internal registers ? detection of ste and lte defects including los, lof, sef, cofa, and ais -l ? fully programmable automatic downstream path ais (ais - p) insertion upon detection of los, lof, tim - s, and/or ais -l ? detection of ste and lte defects including rdi - l, aps unstable, and sync message change (s1) ? detection and accumulation of framing errors (a1/a2), oof occurrences, section bip - 8 (b1) errors (bit or block basis) , line bip - 8 (b2) errors (bit or block basis), and line remote error indications (rei - l) ? extraction of hdlc data stream from section dcc (d1 - d3), line dcc (d4 - d12), toh dcc (d1 - d12), or section user channel (f1) ? extraction of trace id message from section trace (j0) 1.3.7 sts - 1/au - 3/tu -3 pointer processing (ds33m31 and ds33m33 only) 1.3.7.1 sts - 1/au - 3/tu -3 pointer generation ? per sts - 1/au - 3/tu - 3 tributary pointer generation using the associated inbound add sts - 3/stm - 1 clock ? pointer generation per telcordia gr - 253 - core and itu g.707 specifications ? generation of sts - 1, au - 3, or tu - 3 pointer bytes (h1, h2, and h3) and insertion of the sts - 1 spe/vc - 3 poh ? detection and accumulation of pointer increments, decrements, and changes ? user configurable automatic or manual generation of ais -p ? generation of an unequipped indication (all zero path (payload data and poh) with valid j1, b3, and g1) ? comprehensive software programmable pointer (h1, h2) diagnostics (performs a pointer increment justification (pjc+), pointer decrement just ification (pjc - ), pointer change (pjc) to a programmable fixed value (without ndf), or new pointer change (ndf) to a programmable fixed value (with ndf) via the register interface) ? regeneration/relaying of an incoming sts - 1 all - ones pointer (ais - p) withi n one - frame time (125 s ) ? sts- 1 spe poh generation pass - through mode for sts - 1 line terminating equipment (lte) applications downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 10 of 21 1.3.7.2 sts - 1/au - 3/tu -3 pointer interpreter ? per sts - 1/au - 3/tu - 3 tributary pointer interpretation using the outbound drop sts - 3/stm - 1 clock ? pointer interpretati on per telcordia gr - 253 - core and itu g.707 specifications ? extraction of sts - 1, au - 3, or tu - 3 pointer bytes (h1, h2, and h3) ? detection of defects including, lop and all - ones pointer (ais -p) ? detection and accumulation of incoming pointer increments, decrements, changes, and new pointers 1.3.8 sts - 1/vc -3 path termination (ds33m31 and ds33m33 only) 1.3.8.1 sts - 1/vc -3 path overhead generation ? generation of all poh bytes including path trace id (j1), path bip - 8 (b3), path signal label (c2), path status (g1), path user byte (f2), path concatenation indicator (h4), and path growth (z3, z4, and z5) ? all poh bytes can be inserted from either the associated inbound add sts - 1/vc - 3 poh input port or software accessible internal registers ? automatic or manual generation of pte alarm defects including rdi - p and erdi -p ? programmable error insertion of b3 and rei errors ? insertion of hdlc data stream into path user byte (f2) ? insertion of path trace id into path trace byte (j1) 1.3.8.2 sts - 1/vc -3 path overhead reception and monitoring ? termination of all poh bytes (per pte requirement) including path trace id (j1), path bip - 8 (b3), path signal label (c2), path status (g1), path user byte (f2), path concatenation indicator (h4), and path growt h (z3, z4, and z5) ? all poh bytes presented on the associated sts - 1 spe/vc - 3 poh output port and software accessible internal registers ? detection of pte defects: plm - p, plu - p, uneq - p, pdi - p, rdi - p, and enhanced rdi - p (erdi -p) ? detection and accumulation of path b3 and path rei errors (part of g1) on a bit or block basis ? two poh b3 bit error rate (ber) measurement circuits with separate software programmable detecti on and clearing thresholds ? extraction of hdlc data stream from path user byte (f2) ? extraction of path trace id from path trace byte (j1) 1.3.8.3 sts - 1/vc - 3 syn chronizer ? synchronization of sts - 1 spe/vc - 3 to accommodate asynchronous payload through pointer justifications ? accommodation of frequency offsets up to +100ppm between the sonet/sdh telecom bus reference frequency of 77.76mhz and the line/tributary sts - 1 f requency 51.84mhz ? elastic store overflow and underflow conditions ? selectable lock and fast lock modes of operation ? programmable frequency out of range indication ( 5, 10, 20, or 40ppm). ? sonet mapping jitter conforming to gr - 253 and gr - 499 and sdh mapping jitter compliant to itu g.825e and o.172e 1.3.8.4 sts -1 spe payload mapping ? each sts - 1 spe can be mapped with asynchronous ds3/e3 or ethernet traffic. these two mapping modes are mutually exclusive. 1.3.8.5 sts -1 spe ethernet mapping/demapping ? mapping of ethernet pac kets into sts - 1 spe 1.3.8.6 async ds3/e3 demapper/desynchronizer ? extraction of ds3/e3 data stream from an sts - 1 spe compliant to telcordia gr - 253 or vc - 3 compliant to itu g.707 ? generation of a nominal rate e3 (34.368mhz) or ds3 (44.736mhz) ? standard sonet sts - 1 de mapping for a ds3/e3 conforming with telcordia gr - 253 and gr - 499 ? standard sdh vc - 3 demapping for a ds3/e3 conforming to itu - t g.707, g.825e, and o.172e ? all combinations of ds3 or e3 demapping configuration from sts - 1, au - 3, or tu - 3/au - 4 are possible ? softwa re configuration for sonet/sdh demapping on a per tributary basis downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 11 of 21 ? synchronization of ds3/e3 serial streams from sonet/sdh sts - 1 spe/vc - 3 accommodating asynchronous timing between the ds3/e3 line/tributary and the sts - 3/stm -1 references, through appropriate processing of bit stuffing and pointer justifications ? full integration of the ds3/e3 desynchronization and pll circuitry necessary to produce smooth ds3/e3 data and clock signals that meet the telcordia (gr - 253 - core and gr - 499 - core), ansi (t1 - 105.03 - 1994 and t1 - 105.03b - 1997), and itu (g.825e and o.172e) jitter and wander requirements. desynchronize circuitry includes clock smoother consisting of onboard analog/digital control modulators, analog/ digital filters, and frequency detectors ? absorption of sonet/sdh pointer justifications and ds3/e3 payload bit stuffs in an elastic store, and controlling outgoing clock phase using the smooth clock generator circuit with selectable lock and fast loc k modes of operation ? tolerating frequency offsets up to 200ppm between the inbound add telecom bus clock (aclk) and the free - running ds3/e3 reference clocks generated by the internal clock rate adapter ? monitoring and detection of the stability of the recovered ds3 clocks with frequency offset indicati ons of 20, 100, and 200ppm and the elastic store fifo underflow/overflow conditions. the elastic store has an auto center mechanism that separates the read and write pointers under normal operating conditions and after underflow/overflow events occur ? programmable frequency out of range indication ( 10, 20, 40, or 100ppm) ? selectable lock and fast lock modes of operation ? maximum lock time for the smooth recovered/output ds3/e3 data and clock that is demapped from sonet/sdh is 1.06ms (10 ds3, 24 g.751 e3, or nine g.832 e3 frames) (switch time to valid ds 3 with a smooth clock) ? controls include enables/disables/settings for serial data type, and demapping mode 1.3.8.7 async ds3/e3 mapper/synchronizer ? synchronization of ds3/e3 serial streams to sonet/sdh sts - 1 spe/vc - 3 accommodating as ynchronous timing between the ds3/e3 line/tributary and the sts - 3/stm - 1 references, through bit stuffing ? accommodation of frequency offsets up to +200ppm between the 155.52mbps inbound add sts - 3/stm - 1 serial data stream and the 44.736/34.368mhz line/tributary ds3/e3 clock (rlclkn) ? elastic store overflow and underflow conditions ? programmable frequency out of range indication ( 10, 20, 40, or 100ppm) ? sonet mapping jitter conforming to gr - 253 and gr - 499 and sdh mapping jitter compliant to itu g.707, g.825e and o.172e ? mapping of ds3/e3 serial data stream into an sts - 1 spe compliant to telcordia gr - 253 or vc - 3 compliant to itu g.707 ? standard sonet sts - 1 mapping for ds3/e3 conforming to telcordia gr - 253 and gr - 499 ? standard sdh vc - 3 mapping for ds3/e3 conformin g to itu - t g.707 ? all combinations of ds3 or e3 mapping configuration into sts - 1, au - 3, or tu - 3/au - 4 are possible ? software configuration for sonet/sdh mapping on a per tributary basis ? software configuration for all fixed stuff bits to zeros or ones ? controls include enables/disables/settings for mapping type, alarm insertion, stuff bits, frequency offset ( 100ppm to 200ppm) downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 12 of 21 1.4 pdh (ds33m31 and ds33m33 only) there are two sets of ds3/e3 framer/formatters. each set supports three independent ds3/e3 data strea ms (or ports). the set interfaces directly to the async ds3/e3 mapper called add/drop framer/formatter. the set interfaces with external t3/e3 facilities are called line framer/formatter the a dd/drop framers reside in both the ds33m31 and ds33m33 and are used for path monitoring the desynchronized ds3/e3 and test origination of the pdh signals. the line framers, supported only in ds33m33, are used for path monitoring the received signals from external facilities. 1.4.1 add/drop ds3/e3 framer/formatter (ds33m31 and d s33m33 only) 1.4.1.1 drop ds3/e3 framer ? incorporation of drop ds3/e3 framers on a per port basis for far - end alarm detection and performance monitor of ds3/e3 signals that are demapped from sonet/sdh sts - 12/stm -4 ? frame synchronization for m23 ds3, c - bit parity ds3 , g.751 e3, and g.832 e3 ? detection of ds3 loss of frame (lof), out of frame (oof), out of multiframe (oomf), severely error frame (sef), change of frame alignment (cofa), remote defect indication (rdi), alarm indi cation signal (ais), receive unframed all ones, idle signal, ds3 application id bit, and ds3 format mismatch ? detection of g.751 e3 lof, oof, cofa, remote alarm indication (rai), and ais ? detection of g.832 e3 lof, oof, cofa, rdi, and ais ? detection and accumulation of f - bit errors, m - bit errors, fas errors, fa1 and fa2 byte errors, oof occurrences, p - bit parity errors, c - bit parity errors, bip - 8 (bit or block basis) errors, far end block errors (febe), and remote error indications (rei) ? fully programmable automatic ais insertion upon detection of oof and/or ais ? all ds3/e3 overhead fields are presented on the associated receive ds3/e3 overhead output port ? extraction of hdlc data stream from ds3 path maintenance data link (pmdl), g.751 e3 national bit, or g.832 e3 nr or gc bytes ? extraction of trail trace access point identifier from g.832 e3 tr byte 1.4.1.2 add ds3/e3 formatter (optional) ? insertion of all overhead for m23 ds3, c - bit parity ds3, g.751 e3, and g.832 e3 ? manual generation of ais and ds3 idle signals ? automatic or manual generation of rdi/rai and febe /rei ? programmable error insertion of framing errors, parity errors, and febe/rei errors ? all ds3/e3 overhead fields can be sourced from the external transmit ds3/e3 overhead input port ? insertion of hdlc data stream into ds3 path maintenance data link (pmdl), g.751 e3 national bit, or g.832 e3 nr or gc bytes ? insertion of trail trace access point identifier into g.832 e3 tr byte ? m23 ds3 c - bits programmable as payload or overhead ? formatter pass - through mode with programmable ds3 p - bit correction for ds3/e3 line terminating equipment (lte) applications 1.4.1.3 hdlc controller ? two controllers per port for ds3 path maintenance data link (pmdl), g.751 national bit (sn), g.832 nr/gc, or sts - 1 dccs (d1 - d3 and/or d4 - 12), or sts - 1/vc - 3 path user channel (f1 or f2) ? a controller for each optional vc - 4 path user channels (f2) ? 256 - byte receive and transmit fifos ? handles all of the normal layer 2 tasks including zero stuffing/destuffing, fcs generation/checking, abort generation/checking, flag generation/detection, and byte alignme nt ? programmable high and low water marks for the transmit and receive fifos ? rx data is forced to all ones during los, lof, and ais detection to eliminate false packets downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 13 of 21 1.4.1.4 trace identifier controller ? three trace identifier controllers per port for o the line/tributary side g.832 trail trace (tr), o the system/trunk side g.832 trail trace (tr), and system/trunk side sts - 1/vc - 3 path trace (j1) in ds3/e3 mode, or o the sts - 1 section trace (j0), line/tributary side sts - 1 path trace (j1), and system/trunk side sts - 1/ vc- 3 path trace (j1) in sts - 1 mode. ? a trace identifier controller for each optional vc - 4 path trace (j1) ? software programmable trace identifier mode: 16 - byte trail trace access point or 64 - byte path trace ? extraction and storage of the incoming trace iden tifier message in a 64/16 - byte receive register ? software programmable incoming expected trace identifier message ? software programmable outgoing trace identifier message or idle trace identifier message ? incoming trace identifier mismatch, unstable, idle, and change indications ? insertion of the outgoing trace identifier message from a 64/16 - byte transmit register 1.4.1.5 bit error rate tester (bert) ? one bert per port software programmable for insertion o into ds3/e3 payload toward ds3/e3 line interface, or o into ds3 /e3 payload mapped to sts - 1 toward sts - 3/stm - 1 interface, or o into sts - 1 payload toward sts - 3/stm - 1 interface ? generates and detects pseudo - random patterns of length 2n C 1 (n = 1 to 32) and repetitive patterns from 1 to 32 bits in length ? supports pattern insertion/extraction in ds3/e3 payload, or entire data stream ? supports pattern insertion/extraction in sts - 1/vc - 3/vc - 4 payload, or entire sts - 1 spe/au - 3/au - 4 ? large 24 - bit error and 32 - bit bit counters allow testing over long periods without host intervent ion ? errors can be inserted in bert patterns for diagnostic purposes (single bit errors or specific bit - error rates) ? pattern synchronization even in the presence of 10 - 3 bit error rate 1.4.2 ds3/e3 ethernet mapping (ds33m31 and ds33m33 only) ? mapping/demapping of encapsulated ethernet packets into/out - of the payload of the add/drop ds3/e3. 1.4.3 line ds3/e3 framer/formatter (ds33m33 only) 1.4.3.1 line ds3/e3 framer ? frame synchronization for m23 ds3, c - bit parity ds3, g.751 e3, and g.832 e3 ? detection of ds3 loss of signal (los), loss of frame (lof), out of frame (oof), out of multiframe (oomf), severely error frame (sef), change of frame alignment (cofa), remote defec t indication (rdi), alarm indication signal (ais), receive unframed all ones, idle signal, ds3 application id bit, and ds3 format mismatch ? detection of g.751 e3 los, lof, oof, cofa, remote alarm indication (rai), and ais ? detection of g.832 e3 los, lof, oof, cofa, rdi, and ais ? detection and accumulation of f - bit errors, m - bit errors, fas errors, fa1 and fa2 byte errors , oof occurrences, p - bit parity errors, c - bit parity errors, bip - 8 (bit or block basis) errors, far end block errors (febe), and remote error indications (rei) ? fully programmable automatic ais insertion upon detection of los, oof, and/or ais ? all ds3/e3 overhead fields are presented on the associated receive ds3/e3 overhead output port ? extraction of hdlc data stream from ds3 path maintenance data link (pmdl), g.751 e3 national bit, or g.832 e3 nr or gc bytes ? extraction of feac data from ds3 feac bit or g.751 e3 alarm bit ? extraction of trail trace access point identifier from g.832 e3 tr byte ? framer pass - through mode for clear channel applications and externally defined frame formats downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 14 of 21 1.4.3.2 line ds3/e3 formatter (optional) ? insertion of all overhead for m23 ds3, c - bit parity ds3, g.751 e3, and g.832 e3 ? automatic or manual generation of rdi/rai and febe/rei ? fully programmable automatic ais insertion upon detection of an outbound drop telecom bus alarm indication (dalarm), vc - 4 lop, vc - 4 ais - p, sts - 1/au - 3/tu - 3 lop, and/or sts - 1 spe/vc - 3 ais -p ? automatic generation of rdi/rai and febe/rei ? programmable error insertion of framing errors, parity errors, and febe/rei errors ? all ds3/e3 overhead fields can be sourced from the externally controlled transmit ds3/e3 overhead in put port ? insertion of hdlc data stream into ds3 path maintenance data link (pmdl), g.751 e3 national bit, or g.832 e3 nr or gc bytes ? insertion of feac data into ds3 feac bit or g.751 e3 alarm bit ? insertion of trail trace access point identifier into g.832 e3 tr byte ? m23 ds3 c - bits programmable as payload or overhead ? formatter pass - through mode with programmable ds3 p - bit correction for ds3/e3 line terminating equipment (lte) applications 1.4.3.3 feac controller ? one controller per port at the receive ds3/e3 framer and transmit ds3/e3 formatter ? designed to handle multiple feac codewords without host intervention ? receive feac automatically validates incoming codewords and stores them in a 4 - byte fifo ? transmit feac can be programmed to send one code word, one code word continuously, or two different code words back - to - back to send ds3 line loopback commands ? terminates the feac port in ds3 c - bit parity mode or either the sn or a bit in g.751 e3 mode 1.4.3.4 receive b3zs/hdb3 decoder ? software programmable b3zs/hdb3 or ami decodin g ? detection of loss of signal (los) and receipt of b3zs/hdb3 codewords ? detection and accumulation of bipolar violations (bpv), code violations (cv), and excessive z eroes occurrences (exz) 1.4.3.5 transmit b3zs/hdb3 encoder ? software programmable b3zs/hdb3 or ami d ecoding ? programmable insertion of bipolar violations (bpv), code violations (cv), and excess ive zeroes occurrences (exz) 1.4.4 loopback ? line analog terminal loopback alb (transmit liu/line output to receive liu/line input) ? line facility loopback llb (receive liu/line output to transmit liu/line input) ? diagnostic terminal loopback dlb (transmit formatter output to receive framer input) ? payload loopback plb (receive framer output to transmit formatter input) ? sts- 3/stm -1 interface loopback slb (outbound drop telecom bus input to inbound add telecom bus output) ? simultaneous line facility loopback (llb) and diagnostic terminal loopback (dlb) ? optionally ais (unframed all - ones, ua1, or framed ais) can be inserted in the normal data stream during a line (llb), framer diagnostic (dlb), payload (plb), or sts- 3/stm - 1 loopback (slb) mode 1.5 virtual concatenation (vcat) (ds33m31 and ds33m33 only) ? up to three vcg engines 1.5.1 sonet/sdh vcat/lcas ? supports up to three vc - 3 in one vcg (per itu - t g.707) ? supports differential delay compensation up to 200ms downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 15 of 21 1.5.2 pdh vcat/lcas ? supports up to three ds3/e3 in one vcg (per itu - t g.7043/g.7042) ? supports differential delay compensation up to 200ms 1.6 encapsulation ? up to three encap/decap engines for various port configurations 1.6.1 gfp-f encapsulation (pe r itu -t g.7041) ? gfp - f idle frame insertion and extraction ? null header support ? chec- based frame delineation ? x 43 +1 payload scrambling and descrambling ? barker sequence scrambling and descrambling ? supports csf frame handling ? crc - 32 generation and verifi cation 1.6.2 hdlc encapsulation ? programmable 16/32 - bit fcs insertion/extraction ? support for bit and byte stuffed operation ? programmable address/control/pid fields ? self - synchronizing x 43 +1 packet scrambling ? valid and invalid frame counters ? programmable inter - fr ame fill ? frame filtering of fcs errors ? chdlc support with slarp extraction 1.6.3 chdlc encapsulation ? bit stuffing with address/control/pid/fcs fields ? programmable interframe fill length ? transparency processing ? counters: number of received valid frames and erred frames ? incoming frame discard due to fcs error, abort, or frame length longer than preset max ? default maximum frame length is associated with the maximum pdu length of mac frame ? extract slarp for external processor interpretation 1.6.4 x.86 encapsulation support ? transmit transparency processing ? receive rate adaptation removal ? selectable x 43 +1 packet scrambling ? valid and invalid frame counters ? frame filtering of fcs errors 1.7 ethernet feature overview ? supports single 10/100/1000mbps ethernet interfaces (half or full duplex) ? wan packet field modifications (header and fcs) ? byte stuffed hdlc or gfp (null or linear) for any valid bw and vcg size ? ethernet frame modifications (remove 14/18, vlan/q - in - q and ethernet fcs) ? lan frame inspection for vlan (forwarding, discarding, extract), extract, priorit y coding ? wan frame inspection for vlan (forwarding, extract), extract ? scheduler with options of strict priority or wrr ? up to 200ms of differential delay using external ddr sdram ? bridge filtering for 10/100mbps applications ? pol icing based on per - port, per - cos, or per - multicast/broadcast type downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 16 of 21 1.7.1 ethernet mac interface ? one e/fe/gbe port (mii/rmii/gmii) ? 10mbps/100mbps/1000mbps data rates ? support for dte or dce operation ? half - and full - duplex flow control per ieee 802.3 ? jumbo frame le ngths up to 10kb for gbe ? 64 - byte minimum frame size ? ethernet management interface (mdio) ? supports applicable rmon (rfc2819) counters ? promiscuous and broadcast discard modes ? oam frames can be intercepted, processed by host software, and responses inserted 1.7.2 e thernet bridging for 10/100 ? 4k address and vlan id lookup table for learning and filtering ? programmable aging between one to 300 seconds in one - second intervals 1.7.3 ethernet traffic classification ? ingress classification according to ethernet cos ? programmable class map to four queues for each ethernet port 1.7.4 ethernet traffic profiling and policing ? ingress classification by pcp or dscp ? programmable class mapping to four queues ? programmable bandwidth profiling at either the port level or per - class level ? programmable bandwidth profiling for multicast and broadcast flows ? policing with programmable cir/cbs ? nonconforming ethernet frames discarded according to the configured bw profile 1.7.5 ethernet traffic scheduling ? programmable scheduler for ethernet flows toward pdh port(s ): o strict priority, or o weighted queuing 1.7.6 ethernet control frame processing ? control frames, except pause and oam, are forwarded without processing ? pause and oam frames can be programmed to be intercepted, discarded or forwarded 1.7.7 q-in-q ? programmable carrier vlan tag insertion 1.8 sdram interface ? interface for up to 256mb ddr sdram (jedec jesd79d compliant) ? compatible with ddr266+ ? 16 - bit - wide data bus with dual edge transfers and auto refresh timing ? sdram interface clock output of 125mhz ? direct connection to external ddr sdram ? example devices: micron mt46v16m16, samsung k4h561638f and hynix hy5du561622cf 1.9 clock rate adapter (clad) ? creates ds3, e3, sts - 1, and/or telecom bus clocks from single - input reference clock ? input reference clock to clad can be 77.76, 51.84, 44.736, 34.368, or 19.44mhz downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 17 of 21 ? clocks can be used for liu, jitter attenuator, and ds3 desynchronizer reference clocks and sts - 1 transmit clocks on per port basis ? output four derived clocks for external component use, if needed ? meets jitter and wander transmission clock requirements. ? transmit (outbound) line/tributary liu signals using internal clad meet telcordia (ds3) and itu (e3) jitter and wander requirements 1.10 spi serial microprocessor features ? operation up to 10mbps ? burst mode for multibyte read and write ac cesses ? programmable clock polarity and phase ? half - duplex operation gives option to connect sdi and sdo together externally to reduce wire count 1.11 parallel microprocessor interface (ds33m31 and ds33m33 only) ? multiplexed or nonmultiplexed address bus modes ? 8- bit or 16 - bit data bus modes ? intel and motorola bus compatible ? ready handshake output signal ? global reset input pin ? global interrupt output pin ? two programmable i/o pins per port 1.12 test and diagnostics ? ieee 1149.1 jtag support ? diagnostic loopbacks downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 18 of 21 2. standar ds compliance the DS33M30 family of products adhere to the applicable telecommunications standards. table 2-1 provides the specifications and relevant sections. table 2-1 . standards compliance summary specification specification title ansi t1.102 - 1993 digital hierarchy C electrical interfaces t1.105 - 2001 synchronous optical network (sonet) -- basic description including multiplex structure, rates, and form ats t1.105.02 - 2001 synchronous optical network (sonet) C payload mappings t1.105.03 - 1994 synchronous optical network (sonet) C jitter at network interfaces t1.105.03b - 1997 synchronous optical network (sonet) C jitter at network interfaces C ds3 wander s upplement t1.105.06 - 2001 synchronous optical network (sonet) C physical layer specifications t1.107 - 1995 digital hierarchy C formats specification t1.107a - 1990 digital hierarchy C supplement to formats specifications (ds3 format applications) t1.231 - 1997 digital hierarchy C layer 1 in - service digital transmission performance monitoring t1.231.03 - 2003 ds3 C layer 1 in - service digital transmission performance monitoring t1.231.04 - 2003 sonet C layer 1 in - service digital transmission performance monitor ing t1.404 - 1994 network - to - customer installation C ds3 metallic interface specification t1.646 - 1995 broadband isdn C physical layer specification for user - network interfaces including ds1/atm etsi ets 300 337 transmission and multiplexing (tm); generic frame structures for the transport of various signals (including asynchronous transfer mode (atm) cells and synchronous digital hierarchy (sdh) elements) at the itu - t recommendation g.702 hierarchical rates of 2 048 kbit/s, 34 368 kbit/s and 139 264 kbit /s , second edition, june, 1997 ets 300 417 -1-1 generic functional requirements for synchronous digital hierarchy (sdh) equipment , january 1996 ets 300 686 business telecommunications; 34mbit/s and 140mbits/s digital leased lines (d34u, d34s, d140u and d140s); network interface presentation, 1996 ets 300 687 business telecommunications; 34mbit/s digital leased lines (d34u and d34s); connection characteristics , 1996 ets 300 689 business telecommunications (btc); 34 mbit/s digital leased lines (d34u and d34s), terminal equipment interface , v 1.2.1, 2001 - 07 tbr 24 business telecommunications; 34mbit/s digital unstructured and structured lease lines; attachment requirements for terminal equipment interface , 1997 ietf rfc 1662 ppp in hdlc - like framing, july, 1994 rfc 2615 ppp over sonet/sdh; june 1999 rfc 2496 definition of managed objects for the ds3/e3 interface type , january, 1999 rfc 2819 remote network monitoring management information base; may 2000 iso iso 3309:1993 information technology C telecommunications & information exchange between systems C high level data link control (hdlc) procedures C frame structure , fifth edition, 1993 downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 19 of 21 specification specification title itu -t g.703 11/01 physical/electrical characteristics of hierarchical digital interfaces g.704 10/98 syn chronous frame structures used at 1544, 6312, 2048, 8488 and 44 736 kbit/s hierarchical levels g.707/y.1322 network node interface for the synchronous digital hierarchy (sdh) (10/2000) g.751 11/88 digital multiplex equipment operating at the third order bit rate of 34,368 kbit/s and the fourth order bit rate of 139,264 kbit/s and using positive justification g.752 11/88 characteristics of digital multiplex equipments based on a second order bit rate of 6312 kbit/s and using positive justification g .775 11/94 loss of signal (los) and alarm indication signal (ais) defect detection and clearance criteria g.783 02/04 characteristics of synchronous digital hierarchy (sdh) equipment functional blocks g.823 03/00 the control of jitter and wander within digital networks which are based on the 2048 kbit/s hierarchy g.824 03/00 the control of jitter and wander within digital networks which are based on the 1544 kbit/s hierarchy g.825 03/00 the control of jitter and wander within digital networks which are based on the synchronous digital hierarchy (sdh) g.832 10/98 transport of sdh elements on pdh networks C frame and multiplexing structures g.7041/y.1303 generic framing procedure (gfp) (08/2005) g.7042/y.1305 link capacity adjustment scheme (lcas) for virtual concatenated signal (03/2006) g.7043/y.1343 virtual concatenation of pdh signals (07/2004) g.8040/y.1340 gfp frame mapping into pdh (09/2005) o.150 05/96 general requirements for instrumentation for performance measurements on digital tran smission equipment o.151 10/92 error performance measuring equipment operating at the primary rate and above o.161 11/88 in - service code violation monitors for digital systems o.162 10/92 equipment to perform in - service monitoring on 2048, 8448, 34,368 and 139,264 kbit/s signals o.171 04/97 timing jitter and wander measuring equipment for digital systems which are based on the plesiochronous digital hierarchy (pdh) o.172 03/01 timing jitter and wander measuring equipment for digital systems which are based on the synchronous digital hierarchy (sdh) o.181 05/02 equipment to assess error performance on stm - n interfaces q.921 isdn user - network interface C data link layer specification ( 09/1997) y.1731 y.1731 ethernet oam (05/2006) x.86/y.1323 e thernet over laps (02/2001) telcordia gr - 253 - core synchronous optical network (sonet) transport systems: common generic criteria , issue 3, september 2000 gr - 499 - core transport systems generic requirements (tsgr): common requirements, issue 2, december 1998 gr - 820 - core generic digital transmission surveillance , issue 1, november 1994 ieee 802.3 - 2005 csma/cd access method and physical layer specifications. 802.1d - 2004 mac bridge 802.1q - 2005 virtual lans 802.1v - 2001 vlan classification by protocol and port 802.1ag ethernet oam (extract/insert support) (draft 8.1) ieee std 1149 - 1990 ieee standard test access port and boundary - scan architecture, (includes ieee std 1149 - 1993e) october 21, 1993 other rmii: industry implementation agreement for reduced mii interface, sept 1997 downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 20 of 21 3. applications ? ethernet service mux over sdh (eos) higher order ? ethernet service backhaul over pdh over sdh (eopos) e3/t3 ? sts - 1/vc3 ? ethernet service extension ? integrated access device (iad) dual service with data (ethernet) and tdm (e3/ds3) access ? ethernet access concentrators ? mspps with eos and eop support ? base - station backhaul ? microwave radio links figure 3-1 . example application 1: eos for DS33M30 figure 3-2 . example application 2: eopos for ds33m31 interworking with eop in ds33x162 family of devices figure 3-3 . example application 3: eopos transport for ds33m33 with integrated ethernet and pdh services DS33M30 DS33M30 gbe gbe stm-1 eth sw eth sw sdh adm stm-1 ds33m33 gbe eth sw sdh adm stm-1 pdh adm ds3 . . . e1/t1 e/fe . . . ds33m33 gbe eth sw stm-1 (a) (b) pdh mux ds3 . . . e1/t1 e/fe . . . ds33x11/ ds33x41 e/fe/ gbe eth sw eop ds3 ds33x11/ ds33x41 e/fe/ gbe eop e3/t3 1~3 lines, 1 vcg eth sw ds33m31 e/fe/ gbe eth sw sdh adm eopos stm-1 downloaded from: http:///
DS33M30/m31/m33 data sheet rev: 010809 21 of 21 maxim cannot assume responsibility for use of any circuitry other than circu itry entirely embodied in a maxim product. no cir cuit patent licenses are implied. maxim reserves the right to change the circuitry and specificat ions without notice at any t ime. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2009 maxim integrated products is a registered tradem ark of maxim integrated products. 4. revision history revision number revision date description pages changed 0 101508 initial release 1 010809 removed future status in the ordering information table for the ds33m31 and ds33m33 1 downloaded from: http:///

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